Business Wire India
RISC-V Foundation:
WHAT: RISC-V Workshop in Chennai, India
WHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, India
WHEN: Wednesday, July 18 and Thursday, July 19, 2018
DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA). IIT Madras is hosting the event and the lead sponsor is Western Digital.
Western Digital’s Vivek Tyagi, director of business development, embedded and enterprise in India, will present the keynote on Wednesday, July 18. The event will feature a variety of speaking sessions, along with poster presentations and demonstrations. In addition, there will be a panel concluding the first day of the Workshop. The event schedule is as follows:
Wednesday, July 18, 2018:
- RISC-V ISA & Foundation Overview
- RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance
- Going Beyond the RISC-V General Purpose Solutions
- Architecture Exploration of RISC-V Processor and Comparison With ARM Cortex A53 and A72
- It's Not About the Core, It's About the System
- RiTA: RISC-V Trace Analyzer
- Keynote: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures
- Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms and Custom Accelerators
- Mi-V RISC-V Embedded Ecosystem
- Verification of the PULPino SoC Platform Using UVM
- Porting Graphical Stacks to RISC-V Using QEMU and Yocto
- Panel: Evolving a RISC-V based Ecosystem in India
- Poster / Demonstration Previews
- Evening Reception, Poster Sessions and Demonstrations
Thursday, July 19, 2018
- RISC-V Software Development Methodology for RISC-V Devices with RTOS and Linux or Both
- Linux Kernel on RISC-V: Where Do We Stand?
- A Comprehensive Framework for Power-based Side-channel Leakage Evaluation of Shakti C-Class
- RISECREEK: From RISC-V Spec to 22FFL Silicon
- Shakti M-Class Libre RISC-V SoC
- SLSV : The Shakti LockStep Verification Framework
- A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)
- Integrating Gen-Z in Server-Class RISC-V Processors
- Formal Specification of the RISC-V Instruction Set Architecture
- RISC-V Workshop Chennai Conclusion
To register for the event, please visit: https://tmt.knect365.com/risc-v-workshop-chennai/purchase/select-package. To learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-chennai/sponsor-book-stand.
For press interested in attending, please email: risc-v@racepointglobal.com to receive your complimentary pass. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
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Source: Businesswire